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INTEGRATED CIRCUITS
DATA SHEET
UDA1345TS Economy audio CODEC
Product specification Supersedes data of 2000 Dec 19 2002 May 28
Philips Semiconductors
Product specification
Economy audio CODEC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.11 7.11.1 7.11.2 7.11.3 7.11.4 7.11.5 7.12 7.12.1 7.12.2 FEATURES General Multiple format input interface DAC digital sound processing Advanced audio configuration GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog-to-Digital Converter (ADC) Analog front-end Decimation filter (ADC) Interpolation filter (DAC) Double speed Noise shaper (DAC) The Filter Stream DAC (FSDAC) Power control L3MODE or static pin control L3 microcontroller mode Pinning definition System clock Multiple format input/output interface ADC input voltage control Overload detection (ADC) DC cancellation filter (ADC) Static pin mode Pinning definition System clock Mute and de-emphasis Multiple format input/output interface ADC input voltage control L3 interface Address mode Data transfer mode 15.2 15.3 15.4 15.5 16 17 18 8 9 10 11 12 13 14 15 15.1 LIMITING VALUES
UDA1345TS
THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS (ANALOG) AC CHARACTERISTICS (DIGITAL) APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
1 1.1 FEATURES General
UDA1345TS
* Low power consumption * 2.4 to 3.6 V power supply range with 3.0 V typical * 5 V tolerant TTL compatible digital inputs * 256, 384 and 512fs system clock * Supports sampling frequencies from 8 to 100 kHz * Non-inverting ADC plus integrated high-pass filter to cancel DC offset * The ADC supports 2 V (RMS) input signals * Overload detector for easy record level control * Separate power control for ADC and DAC * Integrated digital interpolation filter plus non-inverting DAC * Functions controllable either by L3 microcontroller interface or via static pins * The UDA1345TS is pin and function compatible with the UDA1344TS * Small package size (SSOP28). 1.2 Multiple format input interface 1.4 Advanced audio configuration * Stereo single-ended input configuration * Stereo line output (under microcontroller volume control), no post filter required * High linearity, dynamic range and low distortion. 2 GENERAL DESCRIPTION
* I2S-bus, MSB-justified up to 24 bits and LSB-justified 16, 18 and 20 bits format compatible * Three combined data formats with MSB data output and LSB 16, 18 and 20 bits data input * 1fs input and output format data rate. 1.3 DAC digital sound processing
The UDA1345TS is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. The UDA1345TS supports the I2S-bus data format with word lengths of up to 24 bits, the MSB justified data format with word lengths of up to 20 bits and the LSB justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1345TS also supports three combined data formats with MSB justified data output and LSB 16, 18 and 20 bits data input. The UDA1345TS can be used either with static pin control or under L3 microcontroller interface. In L3 mode the UDA1345TS has basic sound features in playback mode such as de-emphasis, volume control and soft mute.
The sound processing features of the UDA1345TS can only be used in L3 microcontroller mode: * Digital dB-linear volume control (low microcontroller load) via L3 microcontroller with 1 dB steps * Digital de-emphasis for 32, 44.1 and 48 kHz * Soft mute via cosine roll-off (in 1024 samples). Note: in contrast to the UDA1344TS, the UDA1345TS does not have bass-boost and treble. 3 ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME UDA1345TS SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm VERSION SOT341-1
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
4 QUICK REFERENCE DATA SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current 2.4 2.4 2.4 operating mode - ADC power-down - ADC power-down all - operating mode - DAC power-down - operating mode - DAC power-down - operating mode - ADC and DAC power-down - -40 notes 1 and 2 at 0 dB, 1 V (RMS) fs = 44.1 kHz fs = 96 kHz at -60 dB, 1 mV (RMS); A-weighted fs = 44.1 kHz fs = 96 kHz Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz -2.5 PARAMETER CONDITIONS MIN.
UDA1345TS
TYP. 3.0 3.0 3.0 10 600 300 4 50 2.0 200 5 350 - -1.5
MAX. UNIT 3.6 3.6 3.6 14 800 800 7.0 150 3.0 400 8 500 +85 -0.5 V V V mA A A mA A mA A mA A C dBFS
IDDA(DAC) IDDO(DAC) IDDD Tamb Do
DAC analog supply current DAC operational amplifier supply current digital supply current ambient temperature
Analog-to-digital converter digital output level at 1 V (RMS) input voltage (THD + N)/S total harmonic distortion-plus-noise to signal ratio
- -
-85 -80
-80 -75
dB dB
- - 90 90 - 850 - - - - - 90 90
-36 -34 96 94 100 900 -85 -80 -37 -35 100 100 98
-30 -30 - - - 950 -80 -71 -30 -30 - - -
dB dB dB dB dB mV dB dB dB dB dB dB dB
S/N
signal-to-noise ratio
cs
channel separation note 3 at 0 dB fs = 44.1 kHz fs = 96 kHz at -60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz code = 0; A-weighted fs = 44.1 kHz fs = 96 kHz
Digital-to-analog converter Vo(rms) output voltage (RMS value) (THD + N)/S total harmonic distortion plus noise-to-signal ratio
cs S/N
channel separation signal-to-noise ratio
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
SYMBOL Power performance PADDA PDA PAD PPD Notes
PARAMETER power consumption in record and playback mode power consumption in playback only mode power consumption in record only mode power consumption in Power-down mode
CONDITIONS
MIN. - - - -
TYP. 64 36 46 2.2
MAX. UNIT - - - - mW mW mW mW
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage.
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Philips Semiconductors
Product specification
Economy audio CODEC
5 BLOCK DIAGRAM
UDA1345TS
handbook, full pagewidth
VDDA(ADC) VSSA(ADC) 2 1
VADCP 7
VADCN 6
Vref(A) 4
VINL
3
0 dB/6 dB SWITCH
0 dB/6 dB SWITCH
5
VINR
ADC
ADC 8 MC1 MC2 MP5
VDDD VSSD
10 11
DECIMATION FILTER
21 20
DC-CANCELLATION FILTER 18 16 17 19 DIGITAL INTERFACE L3-BUS INTERFACE 13 14 15 12
DATAO BCK WS DATAI
MP2 MP3 MP4 SYSCLK
MP1
9
INTERPOLATION FILTER
UDA1345TS
NOISE SHAPER
DAC VOUTL 26
DAC 24 VOUTR
25 VDDO
27 VSSO
23 VDDA(DAC)
22 VSSA(DAC)
28 Vref(D)
MGS875
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Economy audio CODEC
6 PINNING SYMBOL VSSA(ADC) VDDA(ADC) VINL Vref(A) VINR VADCN VADCP MC1 MP1 VDDD VSSD SYSCLK MP2 MP3 MP4 BCK WS DATAO DATAI MP5 MC2 VSSA(DAC) VDDA(DAC) VOUTR VDDO VOUTL VSSO Vref(D) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 analog ground pad analog supply pad analog input pad analog pad analog input pad analog pad analog pad 5 V tolerant digital input pad with internal pull-down pad 5 V tolerant slew rate controlled digital output pad digital supply pad digital ground pad 5 V tolerant digital Schmitt triggered input pad 3-level input pad 5 V tolerant digital Schmitt triggered input pad 3-level input pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant slew rate controlled digital output pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant digital Schmitt triggered input pad 5 V tolerant digital input pad with internal pull-down pad analog ground pad analog supply pad analog output pad analog supply pad analog output pad analog ground pad analog pad TYPE
UDA1345TS
DESCRIPTION ADC analog ground ADC analog supply voltage ADC input left ADC reference voltage ADC input right ADC negative reference voltage ADC positive reference voltage mode control 1 (pull-down) multi purpose pin 1 digital supply voltage digital ground system clock 256, 384 or 512fs multi purpose pin 2 multi purpose pin 3 multi purpose pin 4 bit clock input word select input data output data input multi purpose pin 5 (pull down) mode control 2 (pull-down) DAC analog ground DAC analog supply voltage DAC output right operational amplifier supply voltage DAC output left operational amplifier ground DAC reference voltage
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Philips Semiconductors
Product specification
Economy audio CODEC
7.1
handbook, halfpage
UDA1345TS
Analog-to-Digital Converter (ADC)
VSSA(ADC) 1 VDDA(ADC) 2 VINL 3 Vref(A) 4 VINR 5 VADCN 6 VADCP 7 MC1 8 MP1 9 VDDD 10 VSSD 11 SYSCLK 12 MP2 13 MP3 14
MGS876
28 Vref(D) 27 VSSO 26 VOUTL 25 VDDO 24 VOUTR 23 VDDA(DAC)
The stereo ADC of the UDA1345TS consists of two 5th-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 64. 7.2 Analog front-end
UDA1345TS
22 VSSA(DAC) 21 MC2 20 MP5 19 DATAI 18 DATAO 17 WS 16 BCK 15 MP4
The analog front-end is equipped with a selectable 0 dB or 6 dB gain block (the pin to select this mode is given in Section 7.10). This block can be used in applications in which both 1 V (RMS) and 2 V (RMS) input signals can be input to the UDA1345TS. In applications in which a 2 V (RMS) input signal is used, a 12 k resistor must be used in series with the input of the ADC. This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1; the power supply voltage is assumed to be 3 V. Table 1 Application modes using input gain stage INPUT GAIN SWITCH 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS)
Fig.2 Pin configuration.
7
FUNCTIONAL DESCRIPTION
The UDA1345TS accommodates slave mode only, this means that in all applications the system devices must provide the system clocks (being the system clock itself and the digital audio interface signals). The system clock must be locked in frequency to the audio digital interface input signals. The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: fBCK 128 x fWS. Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface. Note: the sampling frequency range is from 8 to 100 kHz, however for the 512fs clock mode the sampling range is from 8 to 55 kHz.
RESISTOR (12 k) Present Present Absent Absent 7.3
Decimation filter (ADC)
The decimation from 64fs to 1fs is performed in two stages. sin x The first stage realizes a 4th-order ----------- characteristic. x This filter decreases the sample rate by 8. The second stage consists of 2 half-band filters and a recursive filter, each decimating by a factor of 2.
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
Table 2 Digital decimation filter characteristics CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.05 -60 114 -1.16 7.7
UDA1345TS
The Filter Stream DAC (FSDAC)
ITEM Pass-band ripple Stop band Dynamic range Overall gain when a 0 dB signal is input to ADC to digital output
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is scaled proportionally with the power supply voltage. 7.8 Power control
Note: the digital output level is inversely proportional to the ADC analog power supply. This means that with a constant analog input level and increasing power supply the digital output level will decrease proportionally. 7.4 Interpolation filter (DAC)
The digital filter interpolates from 1 to 128fs by means of a cascade of a recursive filter and an FIR filter. Table 3 Digital interpolation filter characteristics CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC Double speed VALUE (dB) 0.03 -65 116.5 -3.5
In the event that the DAC is powered-up or powered-down, a cosine roll-off mute will be performed (when powering down) or a cosine roll-up de-mute (when powering up) will be performed. This is in order to prevent clicks when powering up or down. This power-on/off mute takes 32 x 4 = 128 samples. 7.9 L3MODE or static pin control
ITEM Passband ripple Stopband Dynamic range Gain 7.5
The UDA1345TS can be used under L3 microcontroller interface mode or under static pin control. The mode can be set via the Mode Control (MC) pins MC1 (pin 8) and MC2 (pin 21). The function of these pins is given in Table 4. Table 4 Mode Control pins MC1 and MC2 MC2 LOW LOW HIGH Static pin mode HIGH MC1 LOW HIGH LOW HIGH
Since the device supports a sampling range of 8 to 100 kHz, the device can support double speed (e.g. for 44.1 kHz and 48 kHz sampling frequency) by just doubling the system speed. In double speed all features are available. 7.6 Noise shaper (DAC)
MODE L3MODE Test modes
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter.
Important: in L3MODE the UDA1345TS is completely pin and function compatible with the UDA1340M and the UDA1344TS. Note: the UDA1345TS does NOT support bass-boost and treble.
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Philips Semiconductors
Product specification
Economy audio CODEC
7.10 L3 microcontroller mode 7.10.5
UDA1345TS
OVERLOAD DETECTION (ADC)
The UDA1345TS is set to the L3 microcontroller mode by setting both MC1 (pin 8) and MC2 (pin 21) LOW. The definition of the control registers is given in Section 7.12. 7.10.1 PINNING DEFINITION
In practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than -1 dB (the actual figure is -1.16 dB) of the maximum possible digital swing. When this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. 7.10.6 DC CANCELLATION FILTER (ADC)
The pinning definition under L3 microcontroller interface is given in Table 5. Table 5 Pinning definition under L3 control DESCRIPTION OVERFL output L3MODE input L3CLOCK input L3DATA input ADC 1 V or 2 V (RMS) input control
SYMBOL PIN MP1 MP2 MP3 MP4 MP5 7.10.2 9 13 14 15 20
An optional IIR high-pass filter is provided to remove unwanted DC components. The operation is selected by the microcontroller via the L3-bus. The filter characteristics are given in Table 6. Table 6 DC cancellation filter characteristics CONDITIONS VALUE (dB) none 0 at 0.00045fs at 0.00000036fs 0 - 0.45fs 0.031 >40 >110
ITEM Pass-band ripple Pass-band gain Droop Attenuation at DC Dynamic range
SYSTEM CLOCK
Under L3 control the options are 256, 384 and 512fs. 7.10.3 MULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The UDA1345TS supports the following data input/output formats under L3 control: * I2S-bus with data word length of up to 24 bits * MSB-justified serial format with data word length of up to 20 bits * LSB-justified serial format with data word lengths of 16, 18 or 20 bits * Three combined data formats with MSB data output and LSB 16, 18 and 20 bits data input. The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed. 7.10.4 ADC INPUT VOLTAGE CONTROL
7.11
Static pin mode
The UDA1345TS is set to static pin control mode by setting both MC1 (pin 8) and MC2 (pin 21) HIGH. 7.11.1 PINNING DEFINITION
The pinning definition under static pin control is given in Table 7. Table 7 Pinning definition for static pin control DESCRIPTION data input/output setting 3-level pin controlling de-emphasis and mute 256fs or 384fs system clock 3-level pin to control ADC power mode and 1 V (RMS) or 2 V (RMS) input data input/output setting
SYMBOL PIN MP1 MP2 9 13 14 15 20
The UDA1345TS supports a 2 V (RMS) input using a series resistor of 12 k as described in Section 7.2. In L3 microcontroller mode, the gain can be selected via pin MP5. When MP5 is set LOW, 0 dB gain is selected. When MP5 is set HIGH, 6 dB gain is selected.
MP3 MP4 MP5
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Philips Semiconductors
Product specification
Economy audio CODEC
7.11.2 SYSTEM CLOCK 7.11.5
UDA1345TS
ADC INPUT VOLTAGE CONTROL
Under static pin control the options are 256fs and 384fs. With pin MP3 (pin 14) the mode can be set as is given in Table 8. Table 8 System clock settings under static pin mode MODE 256fs system clock 384fs system clock 7.11.3 MUTE AND DE-EMPHASIS MP3 LOW HIGH
The UDA1345TS supports a 2 V (RMS) input using a series resistor as described in Section 7.2. In static pin mode the 3-level pin MP4 (pin 15) is used to select 0 or 6 dB gain mode. When MP4 is set LOW the ADC is powered-down. When MP4 is set to half the power supply voltage, then 6 dB gain is selected, and when MP4 is set HIGH then 0 dB gain is selected. Table 11 MP4 mode settings (static mode) MODE ADC Power-down mode 6 dB gain mode 0 dB gain mode MP4 LOW MID HIGH
Under static pin control via MP2 de-emphasis and mute can be selected for the playback path. The definition of the MP2 pin is given in Table 9. Table 9 Settings for pin MP2 MODE No de-emphasis and mute De-emphasis 44.1 kHz Muted 7.11.4 MP2 LOW 0.5VDDD HIGH MULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The data input/output formats supported under static pin control are as follows: * I2S-bus with data word length of up to 24 bits * MSB-justified serial format with data word length of up to 24 bits * Two combined data formats with MSB data output and LSB 16 and 20 bits data input. The data formats can be selected using pins MP1 (pin 9) and MP5 (pin 20) as given in Table 10. Table 10 Data format settings under static pin control INPUT FORMAT MSB-justified I2S-bus MSB output LSB 20 input MSB output LSB 16 input MP1 LOW LOW HIGH HIGH MP5 LOW HIGH LOW HIGH
The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed.
2002 May 28
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andbook, full pagewidth
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Economy audio CODEC
WS 1 BCK DATA MSB 2
LEFT 3 >=8 1 2
RIGHT 3
>=8
B2
LSB MSB
B2 INPUT FORMAT I2S-BUS
LSB MSB
WS 1 BCK DATA MSB B2 2
LEFT 3 >=8 1 2
RIGHT 3 >=8
LSB MSB
B2
LSB MSB MSB-JUSTIFIED FORMAT
B2
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB
WS
LEFT 18 17 16 15 2 1 18
RIGHT 17 16 15 2 1
BCK DATA MSB B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS 20 BCK DATA MSB B2 19
LEFT 18 17 16 15 2 1 20 19 18
RIGHT 17 16 15 2 1
UDA1345TS
Product specification
B3
B4
B5
B6
B19
LSB
MSB
B2
B3
B4
B5
B6
B19
LSB
MGG841
LSB-JUSTIFIED FORMAT 20 BITS
Fig.3 Serial interface formats.
Philips Semiconductors
Product specification
Economy audio CODEC
7.12 L3 interface Table 12 Selection of data transfer BIT 1 0 0 1 1 BIT 0 0 1 0 1
UDA1345TS
The UDA1345TS has a microcontroller input mode. In the microcontroller mode, all of the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: * System clock frequency * Data input format * Power control * DC filtering * De-emphasis * Volume * Mute. The exchange of data and control information between the microcontroller and the UDA1345TS is accomplished through a serial hardware interface comprising the following pins: * L3DATA: microcontroller interface data line * L3MODE: microcontroller interface mode line * L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is LSB first, and is organized in accordance with the so called `L3' format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). The address mode is required to select a device communicating via the L3-bus and to define the destination register set for the data transfer mode. Data transfer for the UDA1345TS can only be in one direction: for the UDA1345TS, data can only be written to the device. Important: since the UDA1345TS does not have a Power-up reset circuit, after power up the L3 interface registers MUST be initialized. 7.12.1 ADDRESS MODE
TRANSFER DATA (volume, de-emphasis, mute, and power control) not used STATUS (system clock frequency, data input format and DC filter) not used
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1345TS is 000101 (bit 7 to bit 2). In the event that the UDA1345TS receives a different address, it will deselect its microcontroller interface logic. 7.12.2 DATA TRANSFER MODE
The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1345TS receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 128fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1345TS after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6.
7.12.2.1
Programming the sound processing and other features
The feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred, being DATA or STATUS. This is performed in the address mode, bit 1 and bit 0 (see Table 12). The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) are the values that are placed in the selected registers. When the data transfer of type DATA is selected, the features Volume, De-emphasis, Mute and Power control can be controlled. When the data transfer of type STATUS is selected, the features system clock frequency, data input format and DC filter can be controlled.
The address mode is used to select a device for subsequent data transfer and to define the destination register set (DATA or STATUS). The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 and 1 indicate the type of subsequent data transfer as given in Table 12.
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
handbook, full pagewidth
L3MODE t h(MA) tLC t s(MA) L3CLOCK tHC t h(MA) t s(MA)
Tcy t s(DAT) t h(DAT)
L3DATA
BIT 0
BIT 7
MGL883
Fig.4 Timing address mode.
handbook, full pagewidth
thalt
thalt
L3MODE tLC t s(MT) tHC Tcy t h(MT)
L3CLOCK
t h(DAT)
t s(DAT)
L3DATA write
BIT 0
BIT 7
MGL884
Fig.5 Timing for data transfer mode.
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
handbook, full pagewidth
thalt
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGD018
Fig.6 Multibyte transfer.
Table 13 Data transfer of type status LAST IN TIME BIT 7 0 BIT 6 0 BIT 5 SC1 BIT 4 SC0 BIT 3 IF2 FIRST IN TIME REGISTER SELECTED BIT 2 IF1 BIT 1 IF0 BIT 0 DC System Clock frequency (5 : 4); data Input Format (3 : 1); DC-filter
Table 14 Data transfer of type data LAST IN TIME BIT 7 0 0 1 1 BIT 6 0 1 0 1 BIT 5 VC5 0 0 0 BIT 4 VC4 0 DE1 0 BIT 3 VC3 0 DE0 0 FIRST IN TIME REGISTER SELECTED BIT 2 VC2 0 MT 0 BIT 1 VC1 0 0 PC1 BIT 0 VC0 0 0 PC0 Volume Control (5 : 0) not used De-Emphasis (4 : 3); MuTe Power Control (1 : 0)
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
7.12.2.2 System clock frequency
Table 18 Volume settings
UDA1345TS
A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 15). Table 15 System clock frequency settings SC1 0 0 1 1 SC0 0 1 0 1 FUNCTION 512fs 384fs 256fs not used
VC5 VC4 VC3 VC2 VC1 VC0 0 0 0 0 : 1 1 1 1 1 1 1 : 0 0 0 0 : 1 1 1 1 1 1 1 : 1 0 0 0 0 : 0 0 0 0 0 1 1 : 1 0 0 0 0 : 0 1 0 0 1 0 0 : 1 0 0 1 1 : 1 0 0 1 1 0 0 : 1 0 1 0 1 : 1 0 1 0 1 0 1 : 1
VOLUME (dB) 0 0 -1 -2 : -50 -52 -54 -57 -60 -66 - : -
7.12.2.3
Data input format
A 3-bit value (IF2 to IF0) to select the used data format (see Table 16). Table 16 Data input format settings IF2 0 0 0 0 1 1 1 1 IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 I2S-bus LSB-justified; 16 bits LSB-justified; 18 bits LSB-justified; 20 bits MSB-justified MSB-justified output/ LSB-justified 16 bits input MSB-justified output/ LSB-justified 18 bits input MSB-justified output/ LSB-justified 20 bits input FUNCTION
1
7.12.2.6
De-emphasis
A 2-bit value to enable the digital de-emphasis filter. Table 19 De-emphasis settings DE1 0 0 1 1 DE0 0 1 0 1 FUNCTION no de-emphasis de-emphasis; 32 kHz de-emphasis; 44.1 kHz de-emphasis; 48 kHz
7.12.2.7 7.12.2.4 DC filter
A 1-bit value to enable the digital DC filter (see Table 17).
Mute
A 1-bit value to enable the digital DAC mute (playback). Table 20 DAC mute
Table 17 DC filtering DC 0 1 FUNCTION no DC filtering DC filtering
MT 0 1
FUNCTION no muting muting
7.12.2.5
Volume control
A 6-bit value to program the left and right channel volume attenuation (VC5 to VC0). The range is 0 dB to - dB in steps of 1 dB (see Table 18).
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
7.12.2.8 Power control
UDA1345TS
A 2-bit value to disable the ADC and/or DAC to reduce power consumption. Table 21 Power control settings FUNCTION PC1 0 0 1 1 PC0 ADC 0 1 0 1 off off on on DAC off on off on
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to ground; VDDD = VDDA = VDDO = 3 V; Tamb = 25 C; unless otherwise specified. SYMBOL VDDD Txtal(max) Tstg Tamb Vesd Ilu(prot) Isc(DAC) PARAMETER digital supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling latch-up protection current short-circuit current of DAC CONDITIONS note 1 MIN. MAX. 5.0 150 +125 +85 200 V C C C mA UNIT - - -65 -40 according to JEDEC II specification Tamb = 125 C; - VDD = 3.6 V Tamb = 0 C; VDD = 3 V; note 2 - output short-circuited to VSSA(DAC) - output short-circuited to VDDA(DAC)
450 325
mA mA
Notes 1. All VDD and VSS connections must be made to the same power supply. 2. DAC operation after short-circuiting cannot be guaranteed. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 90 UNIT K/W
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
10 DC CHARACTERISTICS VDDD = VDDA = VDDO = 3.0 V; fs = 44.1 kHz; Tamb = 25 C; RL = 5 k; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current 2.4 2.4 2.4 - - - - - - - - - 3.0 3.0 3.0 10 600 300 4 50 2.0 200 5 350 3.6 3.6 3.6 14 800 800 7.0 150 3.0 400 8 500 V V V mA A A mA A mA A mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDDA(DAC) IDDO(DAC) IDDD
DAC analog supply current DAC operational amplifier supply current digital supply current
operating mode ADC power-down ADC power-down all operating mode DAC power-down operating mode DAC power-down operating mode ADC and DAC power-down
Digital input pins (5 V tolerant TTL compatible) VIH VIL VIH(th) VIL(th) Vhys ILI Ci VIH VIM VIL VOH VOL Vref(A) Ro(ref) Ri Ci HIGH-level input voltage LOW-level input voltage HIGH-level threshold input voltage LOW-level threshold input voltage Schmitt trigger hysteresis voltage input leakage current input capacitance HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage IOH = -2 mA IOL = 2 mA 2.0 -0.5 1.3 0.9 0.4 - - 0.9VDDD 0.4VDDD -0.5 - - - - - - - - - - 5.0 +0.8 1.9 1.35 0.7 10 10 V V V V V A pF
3-level input pins (MP2; MP4) VDDD + 0.5 V 0.6VDDD V +0.5 V - 0.4 0.55VDDA - - - V V V k k pF
Digital output pins 0.85VDDD - - - 0.45VDDA - - - 0.5VDDA 24 12 20
Analog-to-digital converter reference voltage with respect to VSSA Vref(A) reference output resistance input resistance fi = 1 kHz input capacitance
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
SYMBOL Vref(D) Ro(ref) Ro Io(max) RL CL Notes
PARAMETER
CONDITIONS
MIN. 0.45VDDA - - - 3 -
TYP. 0.5VDDA 12.5 0.13 1.7 - -
MAX. 0.55VDDA - 3.0 - - 200
UNIT V k mA k pF
Digital-to-analog converter reference voltage with respect to VSSA Vref(D) reference output resistance DAC output resistance maximum output current (THD + N)/S < 0.1%; RL = 800 load resistance load capacitance note 2
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven then a 100 resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier.
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19
Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
11 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 3.0 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 C; RL = 5 k; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. -2.5 - - - TYP. -1.5 0.1 -85 -80 MAX. -0.5 - -80 -75 UNIT
Analog-to-digital converter digital output level at 1 V (RMS) notes 1 and 2 input voltage unbalance between channels Vi (THD + N)/S total harmonic distortion-plus-noise at 0 dB, 1 V (RMS) to signal ratio fs = 44.1 kHz fs = 96 kHz at -60 dB, 1 mV (RMS); A-weighted fs = 44.1 kHz fs = 96 kHz S/N signal-to-noise ratio Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz cs channel separation PSRR power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 1% Do Digital-to-analog converter output voltage (RMS value) Vo(rms) unbalance between channels Vo (THD + N)/S total harmonic distortion plus noise-to-signal ratio note 3 at 0 dB fs = 44.1 kHz fs = 96 kHz at -60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz S/N signal-to-noise ratio code = 0; A-weighted fs = 44.1 kHz fs = 96 kHz fripple = 1 kHz; Vripple(p-p) = 1% 850 - - - - - 90 90 - - 900 0.1 -85 -80 -37 -35 100 98 100 60 950 - -80 -71 -30 -30 - - - - mV dB dB dB dB dB dB dB dB dB dBFS dB dB dB
- - 90 90 - -
-36 -34 96 94 100 30
-30 -30 - - - -
dB dB dB dB dB dB
cs PSRR Notes
channel separation power supply rejection ratio
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage.
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20
Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
12 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing; see Fig.7 Tsys system clock cycle fsys = 256fs; note 1 fsys = 384fs; note 1 fsys = 512fs; note 2 tCWL tCWH tr tf tBCK tBCKH tBCKL tr tf ts(DATAI) th(DATAI) fsys LOW-level pulse width fsys HIGH-level pulse width rise time fall time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz 39 26 36 88 59 44 488 325 244 ns ns ns
0.30Tsys - 0.40Tsys - 0.30Tsys - 0.40Tsys - - -
1 128fs
0.70Tsys ns 0.60Tsys ns 0.70Tsys ns 0.60Tsys ns 20 20 - - - 20 20 - - 80 80 - - - - - - - - - - ns ns
- - - - - - - - - - - - - - - - - - - - -
Serial input/output data timing; see Fig.8 bit clock period bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time ns ns ns ns ns ns ns ns ns ns ns ns 34 34 - - 20 0 - - 0 20 10
td(DATAO-BCK) data output delay time (from BCK falling edge) td(DATAO-WS) th(DATAO) ts(WS) th(WS) Tcy tHC tLC ts(MA) th(MA) ts(MT) th(MT) data output delay time (from WS edge) MSB-justified format data output hold time word select set-up time word select hold time
Address and data transfer mode timing; see Figs 4 and 5 L3CLOCK cycle time L3CLOCK HIGH period L3CLOCK LOW period L3MODE set-up time L3MODE hold time L3MODE set-up time L3MODE hold time address mode address mode data transfer mode data transfer mode 500 250 250 190 190 190 190 ns ns ns ns ns ns ns
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Philips Semiconductors
Product specification
Economy audio CODEC
UDA1345TS
SYMBOL ts(DAT) th(DAT) thalt Notes
PARAMETER L3DATA set-up time L3DATA hold time L3MODE halt time
CONDITIONS data transfer mode and address mode data transfer mode and address mode
MIN. 190 30 190 - - -
TYP. - - -
MAX.
UNIT ns ns ns
1. Sampling range from 5 to 100 kHz is supported, with fs = 44.1 kHz typical. 2. Sampling range from 5 to 55 kHz is supported, with fs = 44.1 kHz typical.
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.7 System clock timing.
handbook, full pagewidth
WS tBCKH tr BCK tf th(WS) ts(WS)
td(DATAO-BCK)
tBCKL Tcy DATAO td(DATAO-WS)
th(DATAO)
ts(DATAI) th(DATAI) DATAI
MGL885
Fig.8 Serial interface timing.
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22
Philips Semiconductors
Product specification
Economy audio CODEC
13 APPLICATION INFORMATION
UDA1345TS
The application information as given in Fig.9 is an optimum application environment. Simplification is possible at the cost of some performance degradation. The following notes apply: * The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off frequency of the DC filter also changes. * The capacitors at the input of the ADC can also be reduced. It should be noted that the cut-off frequency of the capacitor with the 12 kW input resistance of the ADC will also change.
handbook, full pagewidth
L1 3V 8LM32A07 L2 8LM32A07 ground C12 100 F (16 V) VDDD C11 100 F (16 V) C2 100 F (16 V) C21 100 nF (63 V) VDDA
VDDA R21 1
VDDD R28 10
R24 10
C25 100 nF (63 V) VADCN 7 VADCP VSSD 11 VDDD 10
VSSA(ADC) VDDA(ADC) system clock R30 47 DATAO BCK WS DATAI SYSCLK 1 12 2 6
18 16 17 19
4
Vref(A) C22 100 nF (63 V) C3 47 F (16 V)
overload flag
MP1
9 26
VOUTL
C5 47 F (16 V) R22 10 k
R23 100
X2
left output
left input
X4
C1 47 F (16 V)
VINL
3
UDA1345TS
24 right input X5 C6 47 F (16 V) MP2 MP3 MP4 13 14 15 27 VSSO C26 100 nF (63 V) C7 100 F (16 V) 25 VDDO 22 VSSA(DAC) C27 100 nF (63 V) C10 100 F (16 V) 23 VDDA(DAC) VINR 5
VOUTR
C8 R27 10 k
R26 100
X3
47 F (16 V)
right output
28
Vref(D) C23 100 nF (63 V) C4 47 F (16 V)
MGS877
R25 1 VDDO
R29 1 VDDA
Fig.9 Application diagram.
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Philips Semiconductors
Product specification
Economy audio CODEC
14 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1345TS
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
2002 May 28
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Philips Semiconductors
Product specification
Economy audio CODEC
15 SOLDERING 15.1 Introduction to soldering surface mount packages
UDA1345TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Economy audio CODEC
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1345TS
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Philips Semiconductors
Product specification
Economy audio CODEC
16 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
UDA1345TS
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/04/pp28
Date of release: 2002
May 28
Document order number:
9397 750 09587

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